Small electronic components, such as semiconductor chips or devices, have their bonding locations for providing electrical connection to external circuitry either on the periphery of one face or in an array spread over a large portion of one face. Devices employing peripheral bonding locations provide only a limited number of access points for electrical connection due to the small area available for such points. Devices employing an array of contact points (also known as "flip chip" devices) overcome this disadvantage by increasing the area available for such points.
Flip chip devices are commonly electrically interconnected to external circuitry by aligning its array of bonding locations, such as metallized bumps, with corresponding bonding locations on the external circuitry and forming a metallurgical bond between the two sets of bonding locations by, for example, reflow soldering, thermocompression bonding, or ultrasonic bonding.
There are at least two serious drawbacks to this interconnection technique. First, there is a large difference in the coefficients of thermal expansion of electronic components such as semiconductor devices typically made from silicon, and external circuitry, such as a ceramic package, typically made from alumina. This difference causes physical stresses on the metallurigical bond between the bonding locations during the thermal cycling encountered during testing and use of the assembled part. The stress must be limited if failure of the metallurigical bond is to be avoided. Commonly the thermal cycling range to be encountered by the assembled part is specified and cannot be limited to less than that specified. Consequently, limiting the stress must be accomplished by limiting the physical magnitude of the stress, typically by limiting the maximum difference in distance between any bonding locations in the array. This limits the size of the array and, consequently, the placement of the bonding locations on the device.
Second, it is normally necessary to remove heat generated during electrical functioning of the semiconductor device. The most effective means of removal is by conducting the heat from the device to the substrate. This is best accomplished by maximizing the contact between the semiconductor device and the ceramic package. However, in the case of flip chip devices, the contact area is limited to the area of the metallurgical bonds. This can be as small as 5% of the area of the device and can cause a severe impairment of removal of heat from the device to the substrate.
The present invention overcomes these disadvantages. It provides a compliant or flexible article which can absorb the stress caused by thermal expansion mismatch. As a result, the bonding locations may be located anywhere on the face of the semiconductor device rather than only in an array of limited size. As a result, more electrical connection points may be provided on a semiconductor device.
The present invention also permits one surface of the device to be placed in maximum contact with the substrate while the bonding locations on the other surface of the device can be placed in thermal contact with the tape, thereby permitting maximum thermal transfer.
Still further the present invention permits direct electrical contact to the back of the device if desired. This is particularly useful when it is desired to electrically ground the device.
The present invention provides still another advantage. Thus, when applied to the electronic component and the external circuitry it protects the assembled device from alpha particles which would otherwise impinge upon the electronic component and undesirably change its electrical state.
Several devices have been previously suggested for interconnecting electronic components to external circuitry. However, these devices have either been intended for use in electrically interconnecting devices which employ peripheral contact points, or they lack one or more of the essential elements of the present invention.
For example, U.S. Pat. Nos. 3,832,769 and 3,868,724 disclose structures wherein a pattern of electrical contacts on one surface are electrically interconnected to a pattern of electrical contacts on another surface. These structures employ only single layers of a dielectric material and a conductive material to join the two patterns of electrical contacts. This type of structure provides only limited space for electrical contact points.
U.S. Pat. No. 4,064,552 describes a tape bearing a foil pattern thereon which has individual electrical terminals to receive components. The foil pattern is on a dielectric carrier and has interlayered connections through apertures in the carrier. The dielectric layers of the tape are adhesively secured to one another.
U.S. Pat. No. 3,780,352 discloses a structure wherein a set of thin metallic film strips are bonded to a thin flexible dielectric support. The metal strips interconnect the contact pads on semiconductor chips and selected leads to electrically interconnect the semiconductor device and the leads.
U.S. Pat. No. 4,251,852 discloses a wiring skirt for electrically interconnecting two identical semiconductor chips to a common set of contacts. The wiring skirt is built in situ around the semiconductor chips.